1. Field of the Disclosure
This specification relates to a shift register, and particularly, to a shift register configuring a gate driver, which is disposed in a flat panel display device such as an organic light emitting diode device to sequentially drive each pixel, a driving method thereof, and a flat panel display device.
2. Background of the Disclosure
Examples of flat panel display (FPD) devices that substitute for cathode ray tube (CRT) display devices, include a liquid crystal display (LCD) device, a field emission display (FED) device, a plasma display panel (PDP) device, an organic light emitting diode (OLED) device, which may be referred to as an organic electroluminescent display (OELD) device, and the like.
Among others, the OLED device has characteristics of high luminance and low operation voltage, and also are self-light emitting devices of generating light by themselves so as to exhibit a high contrast ratio and implement a display with a very thin profile. Also, the OLED device has a fast response time of about several micro seconds (μs), as compared with LCD devices, so as to easily implement a moving picture. The OLED device has additional advantages of an unlimited viewing angle and stability at low temperature.
The OLED device is a current driving type, which represents a gradation of an image by controlling a current which flows on an organic light emitting diode (OLED) disposed on a display panel. In the current driving type, a spot defect (e.g., mura) is caused due to deviations of characteristics of driving transistors for controlling OLEDs. Accordingly, a separate compensation circuit is generally mounted within the display panel to compensate for the characteristic deviation for each driving transistor. The compensation circuit is a sequential compensation type in which pixels on the same horizontal line are driven after being sequentially compensated for by one horizontal period (1h), or a simultaneous emission driving type in which every pixel on a display panel is simultaneously compensated for and driven for one frame.
In the simultaneous emission type, a gate driver which drives pixels on the display panel turns on a switching transistor of each pixel by outputting a gate output voltage (Vout) of high level (VGH) for all of the pixels, and a data driver outputs a predetermined data voltage within one frame. Then, a compensation circuit senses a current flowing through each driving transistor to determine a compensation level of the data voltage for each driving transistor.
Here, the related art gate driver, as shown in FIG. 1, includes a shift register having a plurality of stages 1ST to nST for outputting output voltages Vout to gate lines in synchronization with a clock signal CLK. With the configuration, the first stage 1ST receives a start signal Vst to output a first gate output signal Vout1 of high level for a first horizontal period 1H, and the second stage 2ST receives the first gate output signal Vout1 as the start signal Vst to output a second gate output signal Vout2 of high level. Hence, the second stage 2ST is unable to output the second gate output signal Vout2 if the first stage 1ST does not output the first gate output signal Vout1.
That is, the related art gate driver has the structure of sequentially outputting the gate output signals Vout1 to Vout n by one horizontal period (1H) for one frame. This structure, however, has a limit in that the simultaneous emission type compensation circuit cannot be applied thereto.